List of Tables

Table 1: Notice Icons

Table 2: Text and Syntax Conventions

Table 3: Technical Documentation for Supported Routing Platforms

Table 4: JUNOS Software Network Operations Guides

Table 5: JUNOS Software with Enhanced Services Documentation

Table 6: Additional Books Available Through http://www.juniper.net/books

Table 7: CoS Mappings—Inputs and Outputs

Table 8: Default VPLS Classifiers

Table 9: CoS Hardware Capabilities and Limitations

Table 10: Drop Priority Classification for Packet Sent from Enhanced III to Enhanced II FPC on M320

Table 11: Drop Priority Classification for Packet Sent from Enhanced II FPC Without Tricolor Marking to Enhanced III FPC on M320

Table 12: Drop Priority Classification for Packet Sent from Enhanced II FPC With Tricolor Marking to Enhanced III FPC on M320

Table 13: Routing Engine Protocol Queue Assignments

Table 14: Default CoS Values

Table 15: Default IP Precedence Classifier

Table 16: Default MPLS Classifier

Table 17: Default DSCP Classifier

Table 18: Default IEEE 802.1p Classifier

Table 19: Default IP Precedence (ipprec-default) Classifier

Table 20: Logical Interface Classifier Combinations by Platform

Table 21: Default MPLS EXP Classification Table

Table 22: Default Forwarding Classes

Table 23: Sample Forwarding Class-to-Queue Mapping

Table 24: Buffer Size Temporal Value Ranges by Platform Type

Table 25: Recommended Delay Buffer Sizes

Table 26: Maximum Delay Buffer with q-pic-large-buffer Enabled by Interface

Table 27: Delay-Buffer Calculations

Table 28: NxDSO Transmission Rates and Delay Buffers

Table 29: Scheduling Priority Mappings by FPC Type

Table 30: Shaping Rate and WRR Calculations by PIC Type

Table 31: Transmission Scheduling Support by Interfaces Type

Table 32: Bandwidth and Delay Buffer Allocations by Configuration Scenario

Table 33: Bandwidth and Delay Buffer Allocations by Configuration Scenario

Table 34: Scheduler Allocation for an Ethernet IQ2 PIC

Table 35: RTT Delay Buffers for IQ2 PICs

Table 36: TCM Platform Interoperation

Table 37: Color-Blind Mode TCM Color-to-PLP Mapping

Table 38: Color-Aware Mode TCM PLP Mapping

Table 39: Color-Blind Mode TCM Color-to-PLP Mapping

Table 40: Color-Aware Mode TCM Mapping

Table 41: Tricolor Marking Policer Statements

Table 42: Default Packet Header Rewrite Mappings

Table 43: Default MPLS EXP Rewrite Table

Table 44: Hierarchical Scheduler Nodes

Table 45: Queue Priority

Table 46: Internal Node Queue Priority for CIR Mode

Table 47: Internal Node Queue Priority for PIR-only Mode

Table 48: IQ2 PIC and EQ DPC Compared

Table 49: Shaper Accuracy of 1–Gbps Ethernet at the Logical Interface Level

Table 50: Shaper Accuracy of 10–Gbps Ethernet at the Logical Interface Level

Table 51: Shaper Accuracy of 1–Gbps Ethernet at the Interface Set Level.

Table 52: Shaper Accuracy of 10–Gbps Ethernet at the Interface Set Level.

Table 53: Shaper Accuracy of 1–Gbps Ethernet at the Physical Port Level.

Table 54: Shaper Accuracy of 10–Gbps Ethernet at the Physical Port Level.

Table 55: JUNOS Priorities Mapped to EQ DPC Hardware Priorities

Table 56: Shaping Rates and WFQ Weights

Table 57: Example Shaping Rates and WFQ Weights

Table 58: Rounding Configured Weights to Hardware Weights

Table 59: Allocating Weights with PIR and CIR on Logical Interfaces

Table 60: Sharing Bandwidth Among Logical Interfaces

Table 61: First Example of Bandwidth Sharing

Table 62: Second Example of Bandwidth Sharing

Table 63: Final Example of Bandwidth Sharing

Table 64: LSR Default Classification